Thin film transistor and method of manufacturing the same

ABSTRACT

A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

[0001] This application claims the benefit of Korean patent applicationNo. 96-62231, filed Dec. 6, 1996, which is hereby incorporated byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a thin film transistor of anactive matrix liquid crystal display device and a method ofmanufacturing the same, and, more particularly, to a thin filmtransistor having a double gate layer and a method of manufacturing thesame.

[0004] 2. Discussion of the Related Art

[0005] In general, a thin film transistor (TFT) using amorphous siliconhas an advantage in that a thin film semiconductor layer is formed on aglass substrate by a low-temperature process, and no leakage current isgenerated in the OFF state due to a wide energy band gap and a highresistance of the thin film itself However, because the charge carriermobility in the amorphous silicon of the thin film transistor is low,its current characteristic in the ON state is poor compared to asingle-crystal or polycrystalline transistor. Moreover, the amorphoussilicon thin film transistor does not employ a driving circuit on thesame substrate.

[0006] A thin film transistor using polysilicon has higher chargecarrier mobility and lower resistance than a thin film transistor usingamorphous silicon, thus driving a large current in the ON state andforming a driving circuit with pixels on the same substrate. However,because the polysilicon thin film transistor has a narrow energy bandgap and numerous Si dangling bonds, a large leakage current is generatedaround the drain region.

[0007] Therefore, a thin film transistor was developed having a LDD(lightly doped drain) region, or an offset region, to decrease theleakage current.

[0008]FIG. 1 is a sectional view of a conventional TFT. A buffer oxidelayer 13 is formed on a transparent insulating substrate 11, and asemiconductor layer 15 is formed on a predetermined portion on thebuffer oxide layer 13. A gate oxide layer 17 is formed on apredetermined portion on the semiconductor layer 15. A gate 19 a isformed on a predetermined portion of the gate oxide layer 17.

[0009] The semiconductor layer 15 includes an active region 15 a with noimpurity doping, and an impurity region 15 b where N type or P typeimpurities are highly doped to be used for the source and drain regions.The active region 15 a consists of a channel region C1 where a channelis formed under the gate 19 a, and an offset region O1 between thechannel region C1 and an impurity region 15 b.

[0010] An aluminum gate 19 a is formed overlapping the channel region C1of the active region 15 a. Anode oxide layers 21 and 27 are formed onthe surface of the gate 19 a.

[0011] In the TFT described above, when a voltage is applied to the gate19 a, a channel is formed in the offset region O1 as well as in thechannel region C1 due to an electric field, thereby turning the TFT on.When no voltage is applied to the gate 19 a, no electric field isapplied to the offset region O1, thereby preventing any leakage current.

[0012] FIGS. 2A-2D show the manufacturing process of the TFT. Referringto FIG. 2A, the buffer oxide layer 13 is formed on the transparentinsulating substrate 11. The semiconductor layer 15 is formed on thebuffer oxide layer 13 by depositing polysilicon. The semiconductor layer15 is patterned by a typical photolithography process to expose apredetermined region of the buffer oxide layer 13.

[0013] Referring to FIG. 2B, the gate oxide layer 17 is formed coveringthe buffer oxide layer 13 and the semiconductor layer 15. A gate metallayer 19 is formed by depositing an anode-oxidative metal such asaluminum, and the surface of the gate metal layer 19 is anodized to forma first anode oxide layer 21.

[0014] Referring to FIG. 2C, a photoresist pattern 23 is formed on aportion of the first anode-oxide layer 21. The first oxide layer 21 andthe gate metal layer 19 are anisotropically etched using the photoresistpattern 23 as a mask. A part of the gate metal layer 19 that is notetched and removed becomes the gate 19 a. The second anode oxide layer25 is formed by anodizing the lateral sides of the gate 19 a. The secondanode-oxide layer 25 is anodized in a horizontal direction to define theoffset region O1. In the anodizing process, large current flows to thegate 19 a to speed up the anodizing of the gate 19 a. As a result, thesecond anode oxide layer 25 is porous.

[0015] Referring to FIG. 2D, the gate oxide layer 17 is anisotropicallyetched using the photoresist layer 23 as a mask to expose apredetermined portion of the semiconductor layer 15 and the buffer oxidelayer 13. The photoresist pattern 23 is then eliminated. Next, a thirdanode-oxide layer 27 is formed between the lateral side of the gate 19 aand the second anode-oxide layer 25. Here, an electrolyte liquid makescontact with the lateral side of the gate 19 a through the second porousanode-oxide layer 25 and therefore the third anode-oxide layer 27 isformed by anodizing the gate 19 a. The second anode-oxide layer 25 isetched away, while the first and third anode oxide layers 21 and 27,which are denser than the second anode oxide layer 25, remain during theetching process. The second anode oxide layer 25 is removed entirely.Thus, the third anode-oxide layer 27 remains on the lateral side of thegate 19 a. Thereafter, N type or P type impurities are highly doped intoexposed portions of the semiconductor layer 15, using the first anodeoxide layer 21 and the gate oxide layer 17 as a mask, thus formingsource and drain regions 15 b. Here, the remaining portion of thesemiconductor layer 15 is the active region 15 a. In this active region15 a, the portion overlapping the gate 19 a becomes the channel regionC1, while the portion between the impurity region 15 b and the channelregion C1 is the offset region O1.

[0016] As described above, in the conventional TFT the gate metal layeris patterned using the photoresist pattern 23 as a mask to form the gate19 a, the lateral sides of the gate 19 a are anodized at a high ratewithout eliminating the photoresist pattern in order to form a secondporous anode-oxide layer 25 in a horizontal direction, the photoresistpattern 23 is eliminated, and the portion between the lateral side ofthe gate and the second anode-oxide layer 23 is anodized to form thethird anode-oxide layer. The third anode oxide layer 27 defines theoffset region O1.

[0017] The conventional process for forming a TFT has certain drawbacksbecause it requires a complicated process to eliminate the lateral sideof the gate 19 a after the anodizing in the horizontal direction inorder to define the offset region O1. Also, a hillock is generated dueto the gate 19 a consisting of Al.

SUMMARY OF THE INVENTION

[0018] Accordingly, the present invention is directed to a thin filmtransistor and method of manufacturing the same that substantiallyobviates one or more of the problems due to the limitations anddisadvantages of the related art.

[0019] An object of the present invention is to provide a thin filmtransistor that does not have a hillock due to a gate.

[0020] Another object of the present invention is to provide a methodfor manufacturing a thin film transistor which can reduce the number ofthe processes by facilitating the definition of the offset region.

[0021] Additional features and advantages of the present invention willbe set forth in the description which follows, and in part will beapparent from the description, or may be learned by practice of theinvention. The objectives and other advantages of the invention will berealized and attained by the structure particularly pointed out in thewritten description and claims hereof as well as the appended drawings.

[0022] To achieve these and other advantages and in accordance with thepurpose of the present invention, as embodied and broadly described, ina first aspect of the present invention there is provided a thin filmtransistor including an insulating substrate, a semiconductor layerformed on the insulating substrate and having an active region and animpurity region, a gate insulating layer formed on the active region ofthe semiconductor layer, a first gate metal layer formed on a portion ofthe active region of the semiconductor layer defining a channel region,and a second gate metal layer formed on the first gate metal layer.

[0023] In a second aspect of the present invention there is provided amethod for manufacturing a thin film transistor, including the steps offorming a semiconductor layer on an insulating substrate, wherein thesemiconductor layer has no impurity doping, depositing a gate insulatinglayer, a first gate metal layer and a second gate metal layer on thesemiconductor layer, forming a photoresist pattern on a portion on thesecond gate metal layer, the photoresist pattern overlapping the portionof the semiconductor layer, and etching the first and second gate metallayers using the photoresist pattern as a mask to expose both sides ofthe first gate metal layer to form exposed portions of the first gatemetal layer, wherein the second gate metal layer etches faster than thefirst gate metal layer.

[0024] In a third aspect of the present invention there is provided amethod of manufacturing a thin film transistor, including the steps offorming a semiconductor layer on an insulating substrate, depositing agate insulating layer, a first gate metal layer and a second gate metallayer on the semiconductor layer, forming a photoresist pattern on aportion of the second gate metal layer, the photoresist patternoverlapping a predetermined portion of the semiconductor layer, etchingthe first and second gate metal layers using the photoresist pattern asa mask to expose both sides of the first gate metal layer to form anexposed portion of the first gate metal layer, wherein the second gatemetal layer etches faster than the first gate metal layer, anodizing theexposed portion of the first gate metal layer to form spacers, removingthe photoresist pattern, forming impurity regions by doping impuritiesinto exposed portions of the semiconductor layer, forming an insulatinginterlayer, removing a portion of the insulating interlayer to formcontact holes exposing the impurity regions, forming source and drainelectrodes making contact with the impurity regions through the contactholes, forming a first protective layer on the insulating interlayer andthe source and drain electrodes, forming a light shielding layercovering a portion excluding a pixel region on the first protectivelayer, forming a second protective layer on the first insulating layerand light shielding layer, removing a portion of the first and secondprotective layers to form a contact hole exposing the drain electrode,and forming a pixel electrode on the second protective layer of thepixel region in contact with the drain electrode through the contacthole.

[0025] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are intended to provide further explanation of theinvention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are included to provide afurther understanding of the invention and are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

[0027] In the drawings:

[0028]FIG. 1 is a sectional view of a conventional thin film transistor;

[0029] FIGS. 2A-2D illustrate a conventional process for manufacturingthe thin film transistor of FIG. 1;

[0030]FIG. 3 is a sectional view of a thin film transistor of thepresent invention;

[0031] FIGS. 4A-4D illustrate the process steps for the fabrication ofthe thin film transistor of FIG. 3; and

[0032] FIGS. 5A-5C illustrate the subsequent process steps performedafter the process steps of FIGS. 4A-4D.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0034]FIG. 3 shows a sectional view of a TFT according to the presentinvention. A buffer oxide layer 33 of SiO₂ is formed on a transparentinsulating layer 31, and a semiconductor layer 35 is formed on apredetermined portion of the buffer oxide layer 33.

[0035] The semiconductor layer 35 is formed by depositing polysilicon oramorphous silicon to a thickness between 500 and 1500 Å, and patterningit into a predetermined shape. The semiconductor layer 35 includes of anactive region 35 a having a channel region C2 and an offset region O2where impurities are not doped, and an impurity region 35 b used forsource and drain regions where N type or P type impurities are highlydoped. The channel region C2 is positioned at the center of the activeregion 35 a. The offset region O2 is formed between the channel regionC2 and the impurity region 35 b.

[0036] A gate oxide layer 37 is formed on the active region 35 a on thesemiconductor layer 35 by depositing SiO₂ to a thickness of between 500and 1500 Å.

[0037] A double metal-layered gate 42 comprising first and second gatemetal layers 39 and 41 is formed on the gate oxide layer 37 over thechannel region C2. A spacer 45 is formed on both sides of the first gatemetal layer 39 of the gate over the channel region C2. Here, the firstgate metal layer 39 is formed over the channel region C2 by depositingaluminum to a thickness of between 500 and 4000 Å. The spacer 45, formedon both sides of the first gate metal layer 39 through an anodizingprocess, has a width of between 0.1 and 1 μm. The second gate metallayer 41 is formed on the first gate metal layer 39 by depositingmolybdenum to a thickness of between 500 and 2000 Å, and is used as abarrier to the generation of a hillock due to the diffusion of thealuminum of the first gate metal layer 37 to another insulating layerformed on the first gate metal layer 39.

[0038] In the TFT above, since the first gate metal layer 39 made ofaluminum is surrounded by the second gate metal layer 41 and the spacer45, the hillock cannot be generated. Also, the offset region O1 iseasily defined by the spacer 45.

[0039] FIGS. 4A-4D illustrate the manufacturing process of the thin filmtransistor of FIG. 3.

[0040] As illustrated in FIG. 4A, the buffer oxide layer 33 and thesemiconductor layer 35 are sequentially formed on a transparentinsulating substrate 31. Here, the buffer oxide layer 33 is formed bydepositing SiO₂ by chemical vapor deposition (CVD). The semiconductorlayer 35 is formed by depositing polysilicon or amorphous silicon to athickness of between 500 and 1500 Å and does not contain impuritiestherein. When forming the semiconductor layer 35 of polysilicon, thepolysilicon is deposited by CVD, or formed by depositing amorphoussilicon and then annealing by a laser to crystallize the amorphoussilicon into polysilicon. The semiconductor layer 35 is patterned by atypical photolithographic process to expose a portion of the bufferoxide layer 33.

[0041] As illustrated in FIG. 4B, the gate oxide layer 37 is formed bydepositing SiO₂ through CVD to cover the buffer oxide layer 33 and thesemiconductor layer 35. The a first and second gate metal layers 39 and41 are formed on the gate oxide layer 37 by sequentially depositingaluminum and molybdenum. Here, the first and second gate metal layers 39and 41 are between 500 and 4000 Å thick and between 500 and 2000 Åthick, respectively.

[0042] As illustrated in FIG. 4C, a photoresist pattern 43 is formed onthe second gate metal layer 41. The second and first gate metal layers41 and 39 are sequentially etched to expose the gate oxide layer 37,using the photoresist pattern 43 as a mask. The first and second gatemetal layers 39 and 41 are etched for between 1 and 3 minutes with anetchant containing the mixture solution of H₃PO₄, CH₃COOH and HNO₃.Here, the etchant can etch the molybdenum in the second gate metal layer41 one to ten times faster than the aluminum in the first gate metallayer 39. Therefore, the second gate metal layer 41 is over-etched toexpose both sides of the first gate metal layer 39 by 0.1 to 2 82 m. Thelateral side of the second gate metal layer 41 is etched perpendicularlyor at a slope. The gate oxide layer 37 is dry-etched to expose theactive layer 35 and the buffer oxide layer 33 using the photoresistpattern 43 as a mask.

[0043] As illustrated in FIG. 4D, the exposed portion of the first gatemetal layer 39 is anodized, forming the spacer 45. Here, the remainingfirst and second gate metal layers 39 and 41 are the doublemetal-layered gate 42. Thereafter, the photoresist pattern 43 iseliminated. Even though the spacer 45 is formed using the photoresistpattern 43 in the above description, the spacer 45 can also be formedwithout the photoresist pattern 43.

[0044] N type impurities such as phosphorus, or P type impurities suchas boron are injected by ion doping to form the high impurity regions 35b used for source and drain regions. The remaining portion of thesemiconductor layer 35 is the active region 35 a. In the active region35 a, the portion overlapped by the first gate metal layer 39 is thechannel region C2 and the portion under the spacer 45 is an offsetregion O2. Consequently, the offset region O2 is positioned between theimpurity region 35 b and the channel region C2.

[0045] FIGS. 5A-5C illustrate process steps following the steps of FIGS.4A-4D. As illustrated in FIG. 5A, an insulating interlayer 47 is formedon the resultant structure as shown in FIG. 4D by depositing siliconoxide SiO₂ using CVD. A predetermined portion of the insulatinginterlayer 47 is eliminated by a photolithographic process to form afirst contact hole that exposes the impurity region 35 b. Conductivemetal such as Al, Ti or Cr is deposited and fills up the first contacthole to provide a contact with the impurity region 35 b. A depositedconductive metal layer is patterned to form the source and drainelectrodes 51 and 53. The impurity regions 35 b making contact with thesource and drain electrodes 51 and 53 are the source and drain,respectively.

[0046] As illustrated in FIG. 5B, a first protective layer 55 is formedon the insulating interlayer 47 and the source and drain electrodes 51and 53 by depositing an inorganic insulating substance such as SiO₂ orSi₃N₄, or by coating them with an organic insulating layer including amaterial having a low dielectric constant, such as BCB (Benzo CycloButene), Polyimide with added Fluorine, PCB (Perfluoro Cyclo Butane), orFPAE (Fluoro Poly Allyl Ether). A light shielding layer 57 is formed onthe first protective layer 55 by coating it with an opaque insulatingresin, and then exposing and developing the opaque layer. The lightshielding layer 57 covers the region excluding the pixel region (notshown).

[0047] As illustrated in FIG. 5C, a second protective layer 59 havingthe same insulating material as the first protective layer 59 is formedon the first insulating layer 55 and the light shielding layer 57.Predetermined portions of the first and second protective layers 55 and59 are eliminated in a photolithographic process to form a secondcontact hole that exposes the drain electrode 53. A transparentconductive material such as ITO or SnO₂ is deposited on the secondprotective layer 59 by sputtering to form a contact with the drainelectrode 53 through the second contact hole. The deposited transparentconductive material is patterned to form a pixel electrode 61 in contactwith the drain electrode 53.

[0048] As described above, the thin film transistor of the presentinvention is fabricated as follows. The first gate metal layer 39 ofaluminum and the second gate metal layer 41 of molybdenum aresequentially deposited onto the gate oxide layer 37. The first andsecond gate metal layers 39 and 41 are sequentially etched with anetching solution that etches the second gate metal layer faster than thefirst gate metal layer 39, using the photoresist pattern 43 as a mask,so that a portion of the first gate metal layer 39 is exposed to apredetermined width. Thereafter, the exposed portion of the first gatemetal layer 39 is anode-oxidized to form a spacer 45.

[0049] Therefore, the present invention can prevent the generation ofthe hillock in the first gate metal layer 39 because of the second gatemetal layer 41, and the offset region O1 is easily defined by the spacer45 formed on both sides of the first gate metal layer 39, so that thenumber of process steps is reduced.

[0050] While the invention has been described in detail and withreference to specific embodiments thereof, it will be apparent to oneskilled in the art that various changes and modifications can be madetherein without departing from the spirit and scope thereof Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A thin film transistor comprising: an insulatingsubstrate; a semiconductor layer formed on the insulating substrate andhaving an active region and an impurity region; a gate insulating layerformed on the active region of the semiconductor layer; a first gatemetal layer formed on a portion of the active region of thesemiconductor layer defining a channel region; and a second gate metallayer formed on the first gate metal layer.
 2. The thin film transistoraccording to claim 1 , wherein the first gate metal layer comprisesaluminum.
 3. The thin film transistor according to claim 1 , wherein thefirst gate metal layer has a thickness between 500 and 4000 Å.
 4. Thethin film transistor according to claim 1 , wherein the second gatemetal layer comprises molybdenum.
 5. The thin film transistor accordingto claim 4 , wherein the second gate metal layer has a thickness ofbetween 500 and 2000 Å.
 6. The thin film transistor according to claim 1, further comprising spacers formed on both sides of the first gatemetal layer for defining an offset region.
 7. The thin film transistoraccording to claim 6 , wherein the spacers comprise anodized regions ofthe first gate metal layer.
 8. The thin film transistor according toclaim 6 , wherein the spacers have a width between 0.1 and 2 μm.
 9. Amethod for manufacturing a thin film transistor comprising the steps of:forming a semiconductor layer on an insulating substrate, wherein thesemiconductor layer has no impurity doping; depositing a gate insulatinglayer, a first gate metal layer and a second gate metal layer on thesemiconductor layer; forming a photoresist pattern on a portion on thesecond gate metal layer, the photoresist pattern overlapping a portionof the semiconductor layer; and etching the first and second gate metallayers using the photoresist pattern as a mask to expose both sides ofthe first gate metal layer thereby forming exposed portions of the firstgate metal layer, wherein the second gate metal layer is etched fasterthan the first gate metal layer.
 10. The method according to claim 9 ,wherein the step of depositing the first gate metal layer comprisesdepositing aluminum.
 11. The method according to claim 9 , wherein thestep of depositing the first gate metal layer provides a thickness ofthe first gate metal layer between 500 and 4000 Å.
 12. The methodaccording to claim 9 , wherein the step of depositing the second gatemetal layer comprises depositing molybdenum.
 13. The method according toclaim 9 , wherein the step of depositing the second gate metal layerprovides a thickness of the second gate metal layer between 500 and 2000Å.
 14. The method according to claim 9 , wherein the step of etching thefirst gate metal layer and the second gate metal layer uses a solutioncomprising H₃PO₄, CH₃COOH and HNO₃.
 15. The method according to claim 14, wherein the first and second metal layers are etched for between 1 and3 minutes.
 16. The method according to claim 15 , wherein the secondgate metal layer is over-etched to provide the first gate metal layerwith exposed areas having a width in the range of 0.1 through 2 μm. 17.The method according to claim 9 , further comprising the steps of:anodizing the exposed portions of the first gate metal layer to form aspacer; removing the photoresist pattern; and forming impurity regionsby doping impurities into exposed portions of the semiconductor layer.18. The method according to claim 17 , further comprising the steps of:forming an insulating interlayer over the gate insulating layer and thesemiconductor layer; removing predetermined portions of the insulatinginterlayer to form contact holes exposing areas of the impurity regions;forming source and drain electrodes in contact with the impurity regionthrough the contact holes; forming a first protective layer on theinsulating interlayer and the source and drain electrodes; forming alight shielding layer covering a portion of the first protective layerexcluding a pixel region; forming a second protective layer on the firstinsulating layer and the light shielding layer; removing portions of thefirst and second protective layers to form another contact hole exposingthe drain electrode; and forming a pixel electrode on the secondprotective layer in contact with the drain electrode through the anothercontact hole.
 19. The method according to claim 18 , wherein the firstand second protective layers are selected from a group consisting ofSiO₂, Si₃N₄, and BCB.
 20. A method of manufacturing a thin filmtransistor, comprising the steps of: forming a semiconductor layer on aninsulating substrate; depositing a gate insulating layer, a first gatemetal layer and a second gate metal layer on the semiconductor layer;forming a photoresist pattern on a portion of the second gate metallayer, the photoresist pattern overlapping a predetermined portion ofthe semiconductor layer; etching the first and second gate metal layersusing the photoresist pattern as a mask to expose both sides of thefirst gate metal layer thereby forming an exposed portion of the firstgate metal layer, wherein the second gate metal layer etches faster thanthe first gate metal layer; anodizing the exposed portion of the firstgate metal layer to form spacers; removing the photoresist pattern;forming impurity regions by doping impurities into exposed portions ofthe semiconductor layer; forming an insulating interlayer; removingselected portions of the insulating interlayer to form contact holesexposing the impurity regions; forming source and drain electrodesmaking contact with the impurity regions through the contact holes;forming a first protective layer on the insulating interlayer and thesource and drain electrodes; forming a light shielding layer covering aportion excluding a pixel region on the first protective layer; forminga second protective layer on the first insulating layer and lightshielding layer; removing a portion of the first and second protectivelayers to form another contact hole exposing the drain electrode; andforming a pixel electrode on the second protective layer of the pixelregion in contact with the drain electrode through the another contacthole.